1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including an insulated-gate field effect transistor having a selection gate electrode.
2. Description of the Related Art
A nonvolatile semiconductor memory device is a well-known device among the conventional semiconductor devices. Unlike an EPROM which requires ultra-violet rays for erasing, an electrically erasable and programmable read only memory (EEPROM) has a feature that the memory can be easily treated since data can be programmed with the memory mounted on the board and since a generation circuit for generating high voltages required for erasing and programming and a peripheral circuit thereof are disposed in the memory. Various types of cell structures for the EEPROM are proposed. EEPROMs may be roughly divided into two types, i.e., a floating gate type and a MNOS type. The floating gate EEPROM has a floating gate and electrons are accumulated in a polysilicon layer completely covered with an insulation film in the same manner as in the EPROM. The MNOS type EEPROM traps electrons and holes in the nitride film or in the interface between the oxide film and the nitride film. In either structure, the nonvolatile storing operation is effected by trapping electrons and holes in a portion between the gate and the substrate of the MOS transistor to change the threshold voltage of the MOS transistor.
FIG. 1 shows an example of a conventional floating gate EEPROM cell using a tunnel oxide film and having a stacked gate structure. FIG. 1 is a plan view of a cell portion of the EEPROM. FIG. 2 is a cross sectional view taken along the line I--I' of FIG. 1. As shown in FIGS. 1 and 2, N.sup.+ -impurity diffusion layers 3 and 32 and N.sup.- -impurity diffusion layer 31 are formed in a semiconductor substrate 1 such as a P-polysilicon substrate. An insulation film 8 such as an SiO.sub.2 film is formed on the semiconductor structure. A floating gate electrode 5 and a selection gate 4, both formed of polysilicon, are formed on the insulation film 8. The thickness of the insulation film 8 is approximately 4000 .ANG. (angstroms). The impurity diffusion layers 32 and 3 are disposed on both sides of the electrodes 4 and 5 as the source and drain regions in the semiconductor substrate 1. A control gate electrode 6 of polysilicon is stacked over the floating gate electrode 5 with an inter-level insulation film 11 disposed therebetween. The selection gate electrode 4, and the N.sup.- -impurity diffusion layer 31 and N.sup.+ -impurity diffusion layer 3 which are disposed on both sides of the selection gate electrode 4 are combined to constitute a first insulated-gate field effect transistor (which is hereinafter referred to as a "selection transistor"). The floating gate electrode 5, control gate electrode 6, and the N.sup.+ -impurity diffusion layer 32 and N.sup.- -impurity diffusion layer 31 which are disposed on both sides of the above gate electrodes are combined to constitute a second insulated-gate field effect transistor (which is hereinafter referred to as a "memory transistor"). Part of the insulation film 8 which lies between the gate electrode 5 and the semiconductor substrate 1 of the memory transistor is formed as an oxide film 7 which is as thin as approximately 100 .ANG.. The thin insulation film 7 is called a tunnel oxide film. Electrons can be injected into or emitted from the floating gate electrode 5 by passing a current which causes electrons to be tunneled through the oxide film 7. The erasing operation is effected by applying a high voltage of 15 to 20 V to the control gate electrode 6 and grounding the drain 3 to inject electrons into the floating gate electrode 5. The writing operation is effected by grounding the control gate electrode 6 and applying a high voltage to the drain 3 to emit electrons from the floating gate electrode 5. A plurality of cells described above are connected to word lines and bit lines which are not shown in the drawing and a peripheral circuit such as a high voltage generating circuit is added to constitute the EEPROM described before. As the above floating gate EEPROM, an EEPROM which has the control gate electrode and floating gate electrode arranged on the same plane is provided in addition to the EEPROM with the above stacked structure. In the EEPROM, the surface is made flat but the occupied area becomes large.
However, the EEPROM may not be formed with high integration density because of the presence of the selection gate electrode and it is also difficult to lower the cost thereof. That is, since the distance between the selection gate electrode and the floating gate electrode becomes shorter with an increase in the integration density, the aspect ratio between the gate electrodes becomes higher. The gate electrodes are generally isolated from each other by means of a deposited insulation film of BPSG or PSG. But the deposited insulation film of BPSG or PSG is made partly thin in a portion near the end portions of the gate electrodes. As a result, it may cause a problem that the thin portion of the insulation film may be subjected to dielectric breakdown, or phosphorus contained in the atmosphere at a high density in the reflow step, which is effected in the phosphorus atmosphere after this step, reacts with boron in the BPSG film to form a deposit. The deposit will grow as a projecting portion. The projecting portion may break the metal wiring or short-circuit the metal wirings, thereby lowering the reliability and manufacturing yield of the semiconductor device. Further, when the control gate electrode is formed over the floating gate electrode, the polysilicon film is etched by use of a mask, but the mask which has the same pattern as that of the mask used for forming the floating gate electrode and selection gate electrode is used, and in practice, a polysilicon film having the same pattern as the mask is formed on the selection gate electrode although not shown in the drawing. Generally, the polysilicon film is not removed and is kept as a dummy layer in order to prevent the number of steps from being increased. Therefore, if an insulation film of BPSG or PSG is formed in this position, a deep concave may be formed in the insulation film between the floating gate electrode and the selection gate electrode. As a result, the insulation film may be more easily broken down.
In order to operate the EEPROM in a manner as described before, a high voltage of 15 to 20 V is applied. In this case, if the coupling ratio of the coupling capacitance between the gate electrodes is increased, the operation voltage can be lowered. The coupling ratio CR of a memory transistor of the conventional EEPROM is shown in FIG. 10A. CR indicates the ratio C.sub.2 /(C.sub.1 +C.sub.W +C.sub.31) of a capacitance C.sub.2 between the control gate electrode and the floating gate electrode to the sum of capacitances (C.sub.1 +C.sub.W +C.sub.31) between the floating gate electrode and the semiconductor substrate. Generally, the present coupling ratio is nearly equal to 2. Thus, in a semiconductor device such as an EEPROM having the selection gate electrode, there occurs a problem that the manufacturing yield is lowered and the reliability of the semiconductor device is lowered by breakage or short-circuit of the metal wiring due to deformation of the insulation film caused by an increase in the aspect ratio between the gate electrodes and it is strongly required to lower the operation voltage.